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IDT5V9352 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
INDUSTRIAL TEMPERATURE RANGE
3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
FEATURES:
* Phase-lock loop clock distribution for high performance clock tree applications * Output enable bank control * External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal * No external RC network required for PLL loop stability * Operates at 3.3V/2.5V VCC * Spread Spectrum Compatible * Operating frequency up to 200MHz * Compatible with Motorola MPC9352 * Available in 32-pin TQFP package
IDT5V9352
DESCRIPTION:
The 5V9352 is a low-skew, low-jitter, phase-lock loop (PLL) clock driver targeted for high performance clock tree applications. It uses a PLL to precisely align, in both frequency and phase. The 5V9352 operates at 2.5V and 3.3V.
The 5V9352 features three banks of individually configurable outputs. The banks are configured with five, four, and two outputs. The internal divide circuitry allows for output frequency ratios of 1:1, 2:1, 3:1, and 3:2:1. The output frequency relationship is controlled by the fSEL frequency control pins. The fSEL pins, as well as other inputs, are LVCMOS/LVTTL compatible inputs Unlike many products containing PLLs, the 5V9352 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the 5V9352 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at REFCLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by setting the PLL_EN to high. The 5V9352 is available in Industrial temperature range (-40C to +85C).
FUNCTIONAL BLOCK DIAGRAM
BANK A CCLK REFCLK REF PLL FBIN FB /2 QA3 QA0 1 /2 1 /6 1 QA1 0 0 /4 0 QA2
VCO
PLL_En
QA4
BANK B QB0 VCO_SEL 1 QB1 fSELA 0 QB2
QB3 fSELB BANK C 1 fSELC 0 QC0
QC1
MR/OE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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c 2003 Integrated Device Technology, Inc.
AUGUST 2003
DSC 5973/18
IDT5V9352 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
GND QC1 QC0 GND QB2 QB3 VCC VCC
32 VCO_SEL fSELC fSELB fSELA MR/OE REFCLK GND FBIN 1 2 3 4 5 6 7 8 9
31
30
29
28
27
26
25 24 23 22 21 20 19 18 17 GND QB1 QB0 VCC VCC QA4 QA3 GND
10
11
12
13
14
15
16
PLL_En
QA0
QA1
GND
QA2
VCC
VCCA
TQFP TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC VI IIN IOUT TSTG Rating Supply Voltage Range Input Voltage Range Input Current DC Output Current Storage Temperature Range Max. -0.3 to +3.6 -0.3 to VCC+0.3 20 50 -65 to +125 Unit V V mA mA C
CAPACITANCE
Parameter CIN CPD Description Input Capacitance Power Dissipation Capacitance Min. Typ. 4 10 Max. Unit pF pF
NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress rating only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
LOGIC DIAGRAM(1,2)
RF VCC CF 10nF VCCA
GENERAL SPECIFICATIONS
Symbol VTT HBM LU Description Output Termination Voltage ESD Protection (human body model) Latch-Up Immunity 2000 200 Min. Typ. VCC/2 Max. Unit V V mA
NOTES: 1. IDT5V9352 requires an external RC filter for the analog power supply pin VCCA. 2. For VCC = 2.5V, RF = 9-10, CF = 22F. For VCC = 3.3V, RF = 5-15, CF = 22F.
33...100nF VCC
2
VCC
IDT5V9352 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLES
fSELA 0 1 QAn /4 /6 fSELB 0 1 QBn /4 /2 fSELC 0 1 QCn /2 /4 Control Pin VCO_SEL MR/OE PLL_En Logic 0 fVCO Output Enable Enable PLL fVCO / 2 Outputs disable (high-impedance state) and reset of the device. Disable PLL Logic 1
NOTE: 1. IDT5V9352 requires reset at power up and after any loss of PLL lock. Length of reset pulse should be greater than two REF CLK cycles (REFCLK).
PIN DESCRIPTION
Terminal Name REFCLK FBIN VCCA GND VCO_SEL MR/OE QA (0:4) QB (0:3) QC (0:1) VCC PLL_EN fSEL(C:A) No. 6 8 10 7, 13, 17, 24, 28, 29 1 5 12, 14, 15, 18, 19 22, 23, 26, 27 30, 31 11, 16, 20, 21, 25, 32 9 2, 3, 4 I I PLL enable input. When set LOW, PLL is enabled. When set HIGH, PLL is disabled. Frequency control pin PWR Positive power supply for I/O and core O Clock outputs. These outputs provide low skew copies of REFCLK or can be at different frequencies than REFCLK. I I Allows for the choice of two VCO ranges to optimize PLL stability and jitter performance Allows the user to force the outputs into HIGH impedence for board level test Type I I PWR Ground Description Reference clock input Feedback input. Analog power supply Negative power supply
DC ELECTRICAL CHARACTERISTICS
TA = -40C to +85C, VCC = 3.3V 5%
Parameter VIH VIL VOH VOL ZOUT II ICC ICCA Description Input HIGH Level Input LOW Level HIGH Level Output Voltage LOW Level Output Voltage Output Impedance Input Current(2) Maximum Quiescent Supply Current(3) PLL Supply Current VI = VCC or GND All VCC pins VCCA pin 3 IOH = -24mA IOL = 12mA IOL = 24mA 14 - 17 200 1 5 2.4 0.3 0.55 A mA mA Test Conditions Min. 2 Typ.(1) Max. VCC + 0.3 0.8 Unit V V V V
NOTES: 1. For conditions shown as Min. or Max., use the appropriate value specified under recommended operating conditions. 2. Inputs have pull-down resistors affecting the input current. 3. Icc is the DC current consumption of the device with all outputs open in high-impedance state and the inputs in its default state or open.
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IDT5V9352 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
INDUSTRIAL TEMPERATURE RANGE
INPUT TIMING REQUIREMENTS
TA = -40C to +85C, VCC = 3.3V 5%
Symbol Description /4 feedback /6 feedback REF Reference CLK input in PLL mode(1) Reference CLK input in PLL bypass mode(2) dH tR, tF Input clock duty cycle Maximum input rise and fall times, 0.8V to 2V 25 /8 feedback /12 feedback Min. 50 33.3 25 16.67 Max. 100 66.6 50 33.3 250 75 1 % ns MHz Unit
NOTES: 1. PLL mode requires PLL_EN = 0 to enable the PLL and zero delay operation. 2. In PLL bypass mode, the IDT5V9352 divides the input reference clock.
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IDT5V9352 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS(1)
TA = -40C to +85C, VCC = 3.3V 5%
Symbol tR, tF tSK(O) Characteristic Output Rise/Fall Time Output to Output Skew Test Conditions 0.55V to 2.4V All Outputs, any frequency within QA output bank within QB output bank within QC output bank fVCO PLL VCO Lock Range(2) /2 output /4 output fMAX Maximum Output Frequency /6 output /8 output /12 output tPW tPD tPLZ tPHZ tPZL tPZH tJ Output Duty Cycle REFCLK to FBIN Delay PLL Locked Output Disable Time MR/OE (LOW-HIGH) to any Q Output Enable Time MR/OE (HIGH-LOW) to any Q Output frequencies mixed Cycle-to-Cycle Jitter Outputs in any /4 and /6 combination All outputs same frequency Output frequencies mixed tJ(PER) Period Jitter Outputs in any /4 and /6 combination All outputs same frequency /4 feedback divider RMS (1) tJ() I/O Phase Jitter /6 feedback divider RMS (1) /8 feedback divider RMS (1) /12 feedback divider RMS (1) /4 feedback BW PLL Closed Loop Bandwidth /6 feedback /8 feedback /12 feedback tLOCK Maximum PLL Lock Time
NOTES: 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. The input frequency on CCLK must match the VCO frequency range divided by the feedback divide ratio FB: freq. = fvco / FB.
Min. 0.1
Typ.
Max. 1 200 200 100 100
Unit ns ps
200 100 50 33.3 25 16.67 47 fREF < 40MHz fREF > 40MHz, PLL locked -200 -50 50
400 200 100 66.6 50 33.3 53 +150 +150 8 10 400 250 100 200 150 75 15 20 18-20 25 3 - 10 1.5 - 6 1 - 3.5 0.5 - 2 10
MHz
MHz
% ps ns ns
ps
ps
ps
MHz
ms
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IDT5V9352 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
TA = -40C to +85C, VCC = 2.5V 5%
Parameter VIH VIL VOH VOL ZOUT II(2) ICC(3) ICCA Description Input HIGH Level Input LOW Level HIGH Level Output Voltage LOW Level Output Voltage Output Impedance Input Current Maximum Quiescent Supply Current PLL Supply Current 2 VI = VCC or GND LVCMOS LVCMOS IOH = -15mA IOL = 15mA 17 - 20 200 1 5 Test Conditions Min. 1.7 -0.3 1.8 0.6 Typ.(1) Max. VCC + 0.3 0.7 Unit V V V V A mA mA
NOTES: 1. For conditions shown as Min. or Max., use the appropriate value specified under recommended operating conditions. 2. Inputs have pull-down resistors affecting the input current. 3. Icc is the DC current consumption of the device with all outputs open in High-Impedance state and the inputs in its default state (or open).
INPUT TIMING REQUIREMENTS
TA = -40C to +85C, VCC = 2.5V 5%
Symbol REF Reference CLK input(1) Description /4 feedback /6 feedback /8 feedback /12 feedback Reference CLK input in PLL bypass mode(2) dH tR, tF Input clock duty cycle Maximum input rise and fall times, 0.8V to 2V 25 Min. 50 33.3 25 16.67 Max. 100 66.6 50 33.3 250 75 1 % ns MHz Unit
NOTES: 1. Maximum and minimum input reference is limited by the VCO clock range and the feedback divider. 2. In PLL bypass mode, the 5V9352 divides the input reference clock.
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IDT5V9352 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS(1)
TA = -40C to +85C, VCC = 2.5V 5%
Symbol tR, tF tSK(O) Characteristic Output Rise/Fall Time Output to Output Skew Test Conditions 0.6V to 1.8V All Outputs, any frequency within QA output bank within QB output bank within QC output bank fVCO PLL VCO Lock Range /2 output /4 output fMAX Maximum Output Frequency /6 output /8 output /12 output tPW tPD tPLZ tPHZ tPZL tPZH tJ Output Duty Cycle REFCLK to FBIN Delay PLL Locked Output Disable Time MR/OE (LOW-HIGH) to any Q Output Enable Time MR/OE (HIGH-LOW) to any Q Output frequencies mixed Cycle-to-Cycle Jitter Outputs in any /4 and /6 combination All outputs same frequency Output frequencies mixed tJ(PER) Period Jitter Outputs in any /4 and /6 combination All outputs same frequency /4 feedback divider RMS (1) tJ() I/O Phase Jitter /6 feedback divider RMS (1) /8 feedback divider RMS (1) /12 feedback divider RMS (1) /4 feedback BW PLL Closed Loop Bandwidth /6 feedback /8 feedback /12 feedback tLOCK Maximum PLL Lock Time 15 20 18-20 25 1-8 0.7 - 3 0.5 - 2.5 0.4 - 1 10 ms MHz ps 400 250 100 200 150 75 ps ps 10 ns fREF < 40MHz fREF > 40MHz 200 100 50 33.3 25 16.67 47 -200 -50 50 Min. 0.1 Typ. Max. 1 200 200 100 100 400 200 100 66.6 50 33.3 53 +150 +150 8 ns % ps MHz MHz ps Unit ns
NOTE: 1. AC characteristics apply for parallel output termination of 50 to VTT.
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IDT5V9352 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
IDT5V9352 D.U.T. Pulse Generator Z = 50 ZO = 50 ZO = 50
RT = 50
RT = 50
VTT
VTT
AC Test Reference for VCC = 2.5V and VCC = 3.3V
2V VCC/2 Input 0.8V 1ns 1ns
VCC 2V 0.8V 0V
REF CLK
FBIN tPD
Input Characteristics for 3.3V Prop Delay
1.7V VCC/2 Input 0.7V 1ns 1ns
VCC 1.7V 0.7V 0V
Any Q
Any Q
Input Characteristics for 2.5V
tSK
Skew Calculations
1.8V VCC/2 0.6V Output tR tF
VOH 1.8V 0.6V VOL 0.55V Output tR
2.4V VCC/2
VOH 2.4V 0.55V VOL tF
Output Test Conditions for VCC = 2.5V 5%
Output Test Conditions for VCC = 3.3V 5%
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IDT5V9352 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
INDUSTRIAL TEMPERATURE RANGE
CCLK
FBIN
TJ(0) = T0 - T1 MEAN
I/O Jitter
VCC VCC/2 GND tP T0 tPW = tP/T0 x 100%
Output Duty Cycle
TJ = Tn - Tn+1 Tn Tn+1
Cycle-to-Cycle Jitter
TJ(PER) = Tn - 1/f0 T0
Period Jitter
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IDT5V9352 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXX Device Type XX Package X Process
I
-40C to +85C (Industrial)
PR
Thin Quad Flat Pack
5V9352 3.3V/2.5V Phase-Lock Loop Clock Driver Zero Delay Buffer
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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